I just noticed a discrepancy between the WPC89 and WPC95 schematic with the ASIC chip. Pin 48 and pin 50 are reversed. I'd assume the WPC 95 schematic is correct because it is newer, but I havent checked a real PCB yet.

89 schem left. 95 schem right.
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I believe this is another WPC89 schematic error. On the schematic drawing U17A and U17B need swapped compared to the PCB. U18A and U18B also need swapped on the schematic compared to the drawing.

Proposed corrections in red. This one needs double checked too. Looks like the schematic drawing got penciled in changed but the board didnt update. The WPC95 schem has the gates drawn the same way, so perhaps the change actually happened on later boards?? Might have been last minute change to make the track routing easier.

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Oh wow Zaza i didn't see that picture with the complete pin out because some bonehead marked it as "unsafe picture". I clicked show anyways and then bang.... Nice work. I recreated the entire schematic and that would have helped me out. Some moderator should "un hide" that picture.

Built a WPC 89 prototype today and found that J205 is all mixed on the schematic compared to a real PCB. Pin5 is key, not pin10. Pin10 is ground not pin11.

Looks like Zaza has the direct switches, ground, and the keying corrected on his pin out map. The enable pin is indeed still pin12 (goes to q1).

Have to say the WPC89 original schematic has by far the most errors on it of any pinball pcb i have tried to recreate. I don't think I have ever noticed a problem with old Bally schematics.

I almost wonder if they where worried someone like DE was going to rip off their engineering design again, but I guess that ASIC would be a road block. Probably just a bad schematic drawing and the guy doing the board layout fixed or changed a bunch of stuff that never made it in.

All fixed =D

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I have been professionally trained, by myself =D.

Why does everyone hate right angles on PCB design? The electrons are not going to fly out of alignment.

You should see what the autorouter does when you let it rip. It's like computer generated abstract art.

I am typing in RED, like shown the post I made a few months back, on top of the WPC89 schematic PDF the errors I found which I can probably release.

With Zaza's help, I ~~~ THINK ~~~ , have found them all as i got my WPC89 prototype booting up and playing HSII just fine.

WMS schematic for the RAM chip shows JEDEC pin out. Actual PCB seems to have address bits re-arranged. Zaza's diagram looks like it is correct.

It may not be consistent across every WPC89. Noticed this because I swapped WPC89 CPU boards between drac and HS2. Wanting to retain high scores i moved the NVRAM chip with the ROM but both boards did a restore factory settings on first boot which triggered me to look at the address pins.

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I was wondering if anyone noticed address wire up changes across the different WPC89 revisions. I may have to pull both MPUs out and compare. To the processor it does not care what order the address bits are laid out on the RAM. But if A2 swaps A4 on two different MPUs then the RAM (contents) will not be compatible to move to one board to the other without reformatting to restore factory settings. I think something like that is going on otherwise the NVRAM should be able to move with the ROM to a new board and not get a restore factory settings.

for example if you look at CY6264 they lay out the address bits in a different order than the "jedec" standard.
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For "jedec" it looks like this (which is schematic)
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Ahh, they are different on each board. Never considered that. I backed up the HSII NVRAM with a burner after lost Dracula, so should be able to restore at least one game's memory.