Quoted from elipsitz:Great, thanks! And the typical ~0.6mm header pins should fit through?
As for monitoring the bus, I was thinking that all I really need to do is monitor writes to the 1KB RAM. Then I can have a duplicate view of the memory to read out scores (and maybe other game data) from. In that case, I think I should get by with a GAL to decode the address, R/W, and VMA into a single “writing to ram” signal, then 10 address lines, 8 data lines, the signal from the GAL, and clock/E. That’s 20 signals that can pretty easily go into an ESP32, and it should be fast enough to grab that data.
I looked at just attaching to the display signals, but from a cursory look at the schematic and board, it seems like I’d have to have probes all over the board.
EDIT: Took another look at the display signals. Looks like it’s 16 strobe signals and 8 BCD across two connectors. That’s more signals than reading the bus, but perhaps I could find some 16 input (or 2x8) priority encoder for the strobes to reduce that. Seems a little less fun, but I’ll look into that too.
Reading the displays signals will certainly be easier from a timing point of view. They update much slower than the ram chips, (and you wont have to slow down or interrupt the CPU) but the catch is there won't be anything there to tell you what the number on each display actually means (score vs high score etc, so you'll need to write some code to figure that out. Also, the displays are updated two digits at a time: The left digits of P1 and P3 is updated with one strobe, then the second digits with another. Then P2 + P4 the same way, then credit and match. The timing is fairly consistent so you *could* use only a single strobe line as a cycle restart flag, but it's not perfect and you'll miss digits because of variances in the timing.. If you choose this method you should use all of the strobe lines for accuracy.
Reading the signals for the RAM chip as they come in could be done if the board you design can keep up. To help with address decoding I'd suggest using logic chips to generate a single "Writing to RAM" signal/interrupt to your board. This will save you lots of CPU and interrupts on the board you design. Note also that system 7 RAM chips are actually two 4 bit chips (high and low nibble). The only barrier you might come across in this situation is if the system 7 board is ever wired to use a 6802 CPU. This chip has an onboard 128 bytes of RAM so its unlikely that the chip will still use it's external pins when it accesses those areas, and thus your board may not get to see those areas.