Quoted from adalogue:details about how the address bus is used for PIA chip select
Disclaimer: I'm medical sciences by training and spent a fair amount of time in computer sciences software (often at the assembly level). I only did secondary school level physics. I am not an electrical engineer. The information is provided as-is. I haven't looked at the 6802 code. It's something (along with the 6809 code with WPC) that I want to eventually get to look at it.
If you aren't good with bits and powers of two you probably should try to get comfortable with it. I assume if you're looking at the address bus and decoding that you should be comfortable with this.
Looking at the schematic (sheet 4 of 4 for the CPU board) it appears the PIAs live at $2000 (0x2000 in C hexadecimal representation) with 3 bits of address (10,11,12) selecting five of the PIAs. The remaining PIA is selected with an additional address decode. The six PIAs appear to be located at:
$2100 - sound and solenoids 9-16
$2400 - lamp matrix
$2800 - segments 17-24,strobes 1-16 (a'-g',com')
$2C00 - segments 1-8,9-16 (a-g,com,h-r,dot)
$3000 - switch matrix
$3400 - segments 25-32,sound interface (h'-r',dot')
All the PIAs are selected using A13 ($2000) using pin 24 (CS1). The three bits (10,11,12) are decoded by U37 and used to select the individual PIA using pin 23 (~CS2). It appears the PIAs only recognize two valid address bits (A0,A1). I don't know how those bits are used. I would have to go find some reference manual and read it. Sorry. That's beyond my understanding.
pia_select_common.jpgpia_select_individual.jpg
