I swear I’ve seen one, alas have not found. Anyone have a link or copy they can share? Specifically CPU/RAM/ROM/PIA data lines, chip select, etc. Thanks!
(Topic ID: 268288)
Maidstone
I don't think Williams ever published one of these for System 11. The best source is now probably here
https://pinwiki.com/wiki/index.php?title=Williams_System_9_-_11
If you do find a proper theory of operations, throw a link here somewhere 
Quoted from adalogue:I swear I’ve seen one, alas have not found. Anyone have a link or copy they can share? Specifically CPU/RAM/ROM/PIA data lines, chip select, etc. Thanks!
There was a nice publication on System 9 with the happy pinball working through problems.
System 11 is a superset of system 9 and 7. Most of the information about chips sizes etc. is in the schematics, the special solenoid logic is in the manuals. What information are you seeking?
Oh you know, everything. A page or two on the blanking circuit, details about how the address bus is used for PIA chip select, etc. I’m working on a “signal by signal” summary of a System11 CPU board and couldn’t help but feel like I was wasting time and someone already did.
Clay’s Gide is helpful, so are Leon’s articles on PinWiki, but they are more geared towards repair and not general description of the architecture, circuit topologies, etc.
I’ve since found a lot of helpful info in the MC680x data sheets, might be all that’s out there.
Maybe the Snicer book has some helpful content, will pick up a copy!
Don't overlook the early Data East MPU. It's essentially a clone of the System 11 MPU. The small differences are obvious but there are more detailed decriptions of the board sections in a Data East manual. Laser War and Monday Night Football Football come to mind...
Quoted from snyper2099:Don't overlook the early Data East MPU. It's essentially a clone of the System 11 MPU.
Yes, Stern/DE had the rights to use the physical System 11 architecture but not the software which was written "from scratch" for DE.
Quoted from snyper2099:Don't overlook the early Data East MPU. It's essentially a clone of the System 11 MPU. The small differences are obvious but there are more detailed decriptions of the board sections in a Data East manual. Laser War and Monday Night Football Football come to mind...
Good idea, thanks!
Quoted from adalogue:details about how the address bus is used for PIA chip select
Disclaimer: I'm medical sciences by training and spent a fair amount of time in computer sciences software (often at the assembly level). I only did secondary school level physics. I am not an electrical engineer. The information is provided as-is. I haven't looked at the 6802 code. It's something (along with the 6809 code with WPC) that I want to eventually get to look at it.
If you aren't good with bits and powers of two you probably should try to get comfortable with it. I assume if you're looking at the address bus and decoding that you should be comfortable with this.
Looking at the schematic (sheet 4 of 4 for the CPU board) it appears the PIAs live at $2000 (0x2000 in C hexadecimal representation) with 3 bits of address (10,11,12) selecting five of the PIAs. The remaining PIA is selected with an additional address decode. The six PIAs appear to be located at:
$2100 - sound and solenoids 9-16
$2400 - lamp matrix
$2800 - segments 17-24,strobes 1-16 (a'-g',com')
$2C00 - segments 1-8,9-16 (a-g,com,h-r,dot)
$3000 - switch matrix
$3400 - segments 25-32,sound interface (h'-r',dot')
All the PIAs are selected using A13 ($2000) using pin 24 (CS1). The three bits (10,11,12) are decoded by U37 and used to select the individual PIA using pin 23 (~CS2). It appears the PIAs only recognize two valid address bits (A0,A1). I don't know how those bits are used. I would have to go find some reference manual and read it. Sorry. That's beyond my understanding.
pia_select_common.jpgpia_select_individual.jpgQuoted from DumbAss:It appears the PIAs only recognize two valid address bits (A0,A1). I don't know how those bits are used. I would have to go find some reference manual and read it. Sorry. That's beyond my understanding.
[quoted image][quoted image]
I believe those (RS0 and RS1) are for internal register selection on the PIA. Four internal registers in a 6821, one for group A control, one for group A I/O, one for group B control, and one for group B I/O.
Thanks for your post, it was helpful!
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