Good morning everyone,
Is there any advanced reference material on Stern SAM CPU board ?
I'm specifically looking at block diagram, data flow, etc...
I have looked into the schematics, and I'm trying to make head and tails (plus I think my schematics is missing a section, there's something odd on sheet 1 - I'm using Indiana Jones manual, which has the complete yellow pages...)
I've located the audio section, what I believe the DMD section as well as the memory/flash section.
What's rather complicated to understand is how the main CPU interacts with switchs/coils/etc... it seems the data bus are multiplexed, probably to reduce pin count. I believe the key area is actually page 2, where J9 is located, and all other connectors.
What I'm struggling to understand is as follows:
- what is the FPGA purpose, besides DMD display
- this is a high risk design, sharing a bus for both data output (inserts/coils) and input (switch) seems risky. But since SAM is considered as quite robust, I must have missed something in how it operates
Ultimately, I'd like to understand data output protocol on J9, that's my main focus
If anyone has any expertise on this subject and is willing to participate, I would welcome a discussion
Regards