(Topic ID: 323700)

Stern SAM CPU block diagram

By Ashram56

1 year ago



Topic Stats

  • 8 posts
  • 3 Pinsiders participating
  • Latest reply 1 year ago by Ashram56
  • Topic is favorited by 1 Pinsider

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    #1 1 year ago

    Good morning everyone,

    Is there any advanced reference material on Stern SAM CPU board ?

    I'm specifically looking at block diagram, data flow, etc...

    I have looked into the schematics, and I'm trying to make head and tails (plus I think my schematics is missing a section, there's something odd on sheet 1 - I'm using Indiana Jones manual, which has the complete yellow pages...)

    I've located the audio section, what I believe the DMD section as well as the memory/flash section.

    What's rather complicated to understand is how the main CPU interacts with switchs/coils/etc... it seems the data bus are multiplexed, probably to reduce pin count. I believe the key area is actually page 2, where J9 is located, and all other connectors.

    What I'm struggling to understand is as follows:
    - what is the FPGA purpose, besides DMD display
    - this is a high risk design, sharing a bus for both data output (inserts/coils) and input (switch) seems risky. But since SAM is considered as quite robust, I must have missed something in how it operates

    Ultimately, I'd like to understand data output protocol on J9, that's my main focus

    If anyone has any expertise on this subject and is willing to participate, I would welcome a discussion

    Regards

    #3 1 year ago

    Ah yes, he developed the TLS kit. But I think he focused mostly on switches/inserts readouts, not so much on the CPU/driver board interface, no ?

    1 month later
    #4 1 year ago

    Reviving this thread

    I will hook up a logic analyzer on the data bus to try to understand what's happening. I would welcome some assistance along the way to discuss further, if there are engineers here willing to participate

    Goal is to document on a github how this bus operates, so that the information could be used to build interesting mods on Stern SAM machines

    Cheers

    #6 1 year ago

    Well, I must admit I did know about that But same question apply though, if you have a pointer to Stern Whitestar databus protocol, that would be useful

    That said, I've been looking at the schematics, and on paper it seems relatively straightforward. A 4 bit adress, 8 bit data bus, with decoder which allow to select three solenoid banks, flasher and lamp from what I understand. Still need to understand more on how this operates as a whole, but that does not seem overly complicated, unless I'm missing something

    #8 1 year ago

    Link to github with the result of my analysis of the Stern SAM schematics (I did not even need to hook up a Logic Analyzer, although I will need to at least to know which speed we're talking about)

    https://github.com/Ashram56/Stern-SAM-Databus-Analysis

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