Looking at a serial stream from a single address line isn't super useful.
The real secret sauce is finding the chip enable decodes. A PIA for instance has 3 chip enables CS0, CS1 and CS2 which has a line drawn over it.
A line means active low, no line means active high. So in order to access the PIA the address lines go through some logic to set CS0 and CS1 high, CS2 low and boom! The PIA now accepts I/O.
This is how any IC is selected on the bus. Anything that's not active goes "tristate" meaning its pins aren't affected (and can't affect) the rest of the bus.
Depending on how many channels your scope has you can set logic triggers to look for these states. IE, if channel 1 is high and channels 2 and 3 are low then trigger. This would allow you to pause the scope when a PIA access takes place for instance.
If you lack the channels you can go super dorky and use glue logic to make an edge detector. In the case of the PIA you'd put CS1 and CS0 through an AND gate, CS2 through an inverter, then both of those outputs through another AND gate. This would create a signal that goes high whenever CPU is trying to access PIA. You could use this as an external trigger for the scope and probe signals to see what's happening when the PIA is pinged.