Consolidated v3 conversion steps:
1) Follow the core of the conversion guide in bulletin #6: http://www.sternpinball.com/downloads/sb6.pdf
....a) Remove jumpers J5B and J6B at location D8
....b) Install jumpers J5A and J6A at B7 and D7
....c) Add 3 pins to CN3 (top-right of board)
....d) Remove the EPROM from the socket at position B5 (if any)
2) Install Laser War ROM (http://mirror2.ipdb.org/files/1415/Data_East_1987_Laser_War_ROMs_V1_00.zip)
....a) *IF* using 27512 (64KB) EPROM
........i) Remove jumper J4 and install jumper J5
........ii) Double up Laser War ROM using the copy /b command in the Windows' command prompt
............1) copy /b LWARv1.C5 + LWARv1.C5 LWAR64.C5
........iii) Burn ROM (LWAR64.C5) to a 27C512 or 27512 and install into socket at position C5
....b) *IF* using 27256 (32KB) EPROM (not recommended)
........i) Remove jumper J5 and install jumper J4
........ii) Burn ROM to a 27256 or 27C256 and install into socket at position C5
I went with option 2.a as it permits me to easily swap in test ROMs such as Leon's ROM or DataEast's test ROM. Use these ROMs for extensive diagnostics of your v3 MPU board.
1) Leon's ROM and instructions: http://home.scarlet.be/~fb054529/dataeast/edataeast.htm
2) DataEast's in-houes test ROM (search for detest.zip if link is broken): http://www.vpforums.org/index.php?app=downloads&showfile=811
Instructions for using DataEast's test ROM:
"The test EPROM for DataEast/Sega CPU boards has the following functions. When the Test EPROM is installed into a CPU board and power applied, the CPU will perform power-up self tests and then immediately go into burn-in cycles with no intervention. It is not required that the Test button be pressed in order to initiate burn-in cycles.
The power up self-test will check major components on the CPU board and flash the LED as each one appears normal. If any fail, the LED will stay on. The tests consist of a checksum test of the ROM and read/write test of the RAM and the PIA's. The PIA test will NOT check both sides of all PIA's since certain PIA ports are designed to be inputs and the loading on those ports will determine the data seen by the CPU. However, those ports designed to be outputs will be written to and read from in order that basic go/no-go functionality can be checked.
Flash Chip Location Tested
1 C5 (ROM checksum) 2 D5 (RAM read/write) 3 5F (PIA1 solenoid read/write $2100) 4 8H (PIA5 switch read/write $3002) 5 11D (PIA2 lamp read/write $2402) 6 11B (PIA3 display2 read/write $2802) 7 9B (PIA4 display1 read/write $2C02) 8 7B (PIA6 sound read/write $3402)
The burn-in test will cycle through the solenoids, lamps, display and sounds like the present burn-in, with the following exceptions.
- The solenoid cycling will go through all the solenoid matrix positions.
- The lamps will go through all the patterns of rows and columns, as well as individual lamps; any shorts or opens will be easily seen on a test set lamp matrix board.
- If any matrix switches become closed, the lamp patterns will stop for a time. The lamp(s) corresponding to the matrix position of any closed switch(es) will be turned on. This faciliates testing of the switch matrix. A short time after the switch matrix becomes clear the lamps will go back to patterns. This also means that if any switch matrix position appears closed on power-up, the corresponding lamps will be turned on after the power-on self tests for a visual indication of where problems are located.
Neil Falconer, DataEast 1/6/93"