I have learned more about electronics and logic in the past two weeks than I could have ever imagined, while trying to troubleshoot this Whirlwind System 11B MPU.
OK, so when I turn on the machine, I'm getting a condition where ALL of the solenoids at 1J21 are locking on -- or they don't work at all (there are similar other issues with groups of solenoids and no music). I used Leon's chips and a series of manual tests in diagnostic mode with various solenoids to confirm that the PIA chips are sending the proper signal when called for by the CPU, and all of the transistors/GATE chips are performing correctly.
The odd behavior I'm seeing in this case, doesn't correlate with MD0 through MD4 at PIA U42 (the signal outputs for the 5 solenoids), but rather at the downstream U1 74LS374 chip on the sound solenoid overlay board, where the flip-flop outputs are connecting to a clock and the blanking circuit (output control).
1.) In the case of both lock on and non-working states (using attract mode as an example) the input pins are correctly HI (disabled). The output control (pin 1), associated with the blanking signal input, probes LO which is correct.
2.) According to page 83 in the Whirlwind manual, the clock signal is comprised from a bunch of logic chip switches on a 74LS332 chip coming from signals MD5, MD6, MD7 and MCB2 off of PIA U42 on the MPU (MD0 through MD4 are the solenoids). While the clock signal appears to probe "HI" in both the working and non-working states, I observed that some of these input signals are HI in the non-working state and pulsing in the LOCKED-ON state.
3.) Here's where it gets strange. In the case of the non-working state, the input (D) pins are high and the output pins are high (makes sense). In the case of the locked-on solenoids, the input is high and the output is low -- which trips all the downstream transistors.
How can I have a HI input (D) and a LO output (Q) at each set of pins on U1, unless the chip was somehow "locked" in that state?
Am I also reading the spec right that some of these signals are actually coming not only from 1J21 (U42) on the MPU but also from U4 on the sound solenoid overlay board, with the direction controlled by pin 1 on U4 (DIR)? I'm noticing this pin (which also correlates to MCB2) is changing signals on the differing solenoid states.
I'm like 100% certain the U1/U4 chip on the sound solenoid overlay is good because this board works in another game. So, I'm left to figure out what's going on with these other signals and how they are supposed to read. I'm not getting any errors at boot up, so am I correct that it's not a ROM issue?