I hope everyone had a great festive season! My travel is complete and it is now the adjustment phase. With a fair amount of time off, the build queue is long - both bare and complete. I appreciate everyone's patience in both answering messages, but more importantly as I work through the workload that is ahead. I do also want to finish some of the investigative tasks I had started (the unified System 3 to 7 board), as well as having to handle local requests for board repair and home repair visits. Thankfully, both of those don't happen often but I do have some of those items waiting.
The remainder of this post will be quite technical. Feel free to stop reading now.
Results are shown, but it might also tickle the reader's interest in both how some things work and how I do some aspects of building / engineering. Some things I do might be considered overkill, but sometimes you have to return to basics to know what's going on. This is particularly so when you don't have a single machine low level debugger (or debugger nub).
Let's get started.
This continues from the last big post about verifying the unified System 3 to 7. I wanted to establish the address map is correct, as well as access to the diagnostic LED (System 6) and diagnostic digit (System 7). There are four distinct tests below. I have not tested the bank feature (multiple game ROMs on a single 27C080). I will leave that until later as I need to get a single game ROM executing properly first.
The RAM test.
The system has two separate RAMs. System 6 has SRAM at $0000-$00FF backed by 2x 6810 ICs each holding 128x 8-bit data elements. System 7 has XRAM (SRAM) at $1000-$13FF backed by 2x 2114 ICs each holding 1024x 4-bit data elements. Both have CMOS at $0100-$01FF backed by 1x 5101 IC holding 256x 4-bit data elements. To maintain System 6 compatibility in System 7, the first $100 bytes of XRAM is double-mapped at $0000 serving as the SRAM.
This is the code.
unified3to7_ramtest_code.jpg
This is the result.
unified3to7_ramtest_sram.jpg
unified3to7_ramtest_cmos.jpg
The ROM test.
The OEM board supports multiple ROMs at specific addresses, as well as multiple IC types (2316 vs 2716 or 2532 vs 2732). It's all very confusing. It's much easier to just use a contiguous address space from $4000-$7FFF or $C000-$FFFF. This test records the PC (program counter) in the XRAM to make sure the processor is executing as expected.
This is the code.
unified3to7_romtest_code.jpg
This is the result.
unified3to7_romtest_CD.jpg
unified3to7_romtest_EF.jpg
The diagnostic LED test.
System 6 boards have two LEDs (LED1 and LED2) used for diagnostic indications. This test just makes sure that both of them can be accessed and display correctly.
This is the code.
unified3to7_6led_code.jpg
These are the results.
unified3to7_6led_1.jpg
unified3to7_6led_2.jpg
The diagnostic DIGIT test.
System 7 boards removed the two LEDs and replaced it with a 7-segment digit for diagnostics indication. This test just makes sure that the digit responds correctly. All the digits are correct but only 4, 5 and 6 are shown.
This is the code.
unified3to7_7digit_code.jpg
These are the results.
unified3to7_7digit_4.jpg
unified3to7_7digit_5.jpg
unified3to7_7digit_6.jpg
The basics of the address space work fine. The diagnostic indicators work fine as well. There must be something else wrong on the board. After staring at the schematic even more (prior to travel), I think I have isolated a difference. I need to figure out how to "patch" the fix into the board. I've done this before with cutting traces and such but this time I had a few "pass through with interception digital logic" boards made. These small boards allow me to selectively pass some signals through and intercept (re-route) others. These should help reduce the clutter of cables that I would normally have to construct when testing. I can use these boards in the future when troubleshooting, so it's win-win. While waiting for these boards, I will pick off items in the build queue. Always work to do.