Thanks for all the kind words!
I finished a pack batch over the weekend and I have a small number of left over boards that are a part of orders that were waiting for components that arrived yesterday.
I also got some boards in (locally) that needed repair. I am always scared when I see previous repairs. They are often (not always) poorly done and have residual problems. I always suspect prior work/repairs and though I don't like being so cynical it's unfortunately proven to be true quite often. This particular board was interesting. The short (no pun intended) of the problem was that whoever did the repair tied D1 and D6 together so whenever solenoid 2 fired then both solenoid 2 and 7 would fire. Whenever solenoid 7 fired both solenoid 2 and 7 would fire. Same with solenoid 10 and 15 as well as 18 and 23 as well as 26 and 39. It also wreaked havoc on the lamp matrix as you can imagine. I usually like to clean up repairs better than this but the use of the SIP sockets means I won't touch it and only do the minimal amount of work. I stay far away from repairs that use SIP sockets.
Before:
01_repair_before.jpg
After:
02_repair_after.jpg
In between these small tasks I spent some time on the unified System 3-7 board. It was definitely rushed as there are some interesting problems. Ultimately there's a fundamental problem in this REV-00 that will prevent System 7 boards from working at all. System 6 boards should work but alas ... neither of them work.
Technical summary of state for those interest:
- The address for the SRAM region of the address map is not correct. Williams made a change to System 7 that I didn't factor in. This is due to my ignorance of System 3-7 in general. It also definitely does NOT help that I do not have working System 6 or System 7 boards as a control ("gold standard"). I may eventually need a set if I can't figure things out but I'm not at that stage ... yet.
- The diagnostics for System 6 (two LEDs) and System 7 (digit) are not correct. They're reversed. I read "7400" and thought "AND" but it's actually "NAND" so the BCD to the 7447 is inverted. The System 6 LEDs are reversed as well.
- The good news is that the Leon works. That means the CPU is executing and the basics of address decode is working.
- The bad news is that the ~BLANKING signal stays low (active) and there is no activity on the strobe lines. This is a good indicator that the software is either hung or in some form of infinite loop. The error in SRAM mapping should not affect System 6 execution so this is puzzling to me. This needs more investigation.
The (Williams) universal numeric display works but has a signal input error. I swapped the BCD inputs so there is a workaround that does not require a new board but there is also some other small issue I need to investigate on the board that may require a revision either way. A feature I (attempted) to add to this board is brightness adjustment and it does work but requires more components. The workaround (cable) is shown in the following image.
boards_226.jpg
I generally take my time when trying to figure out problems. I don't always get things immediately and sometimes it takes a while for the penny to drop. This is why things take time for me to do. I am guessing that I will spend a little more time looking at some of these outstanding issues to make a decision on if I need a new board revision. I like to get board fabrication orders sent with priority because while being fabricated I can do something else. If I reverse that order of operation and build first before fabrication I can potentially spend time waiting for fabrication that could be used in other better ways. A little like overlapped I/O for those familiar with old Windows programming.
<tl;dr>
For those that like to read large wads of text with nothing better to do and are interested in the differences between System 6 and System 7 SRAM ... read on.
- System 6 has two physical RAM ICs of $0080 (128) bytes in size mapped at $0000-$007F and $0080-$00FF. They form a single logical unit of $0100 (256) bytes (JBOD in RAID terminology). The CMOS IC is $0100 (256) nibbles (4 bits not 8 bits) used to hold settings and is mapped at $0100-$01FF.
- System 7 has two physical RAM ICs of $0400 (1,024) nibbles in size mapped at $1000-$13FF. Each nibble of the byte is written to different units (striping in RAID terminology). The CMOS IC is the same ($0100 nibbles mapped at $0100-$01FF). To maintain compatibility with System 6 the hardware maps $0000-$00FF to the first $0100 bytes of the regular RAM - in essence a double mapping (two addresses map to the same physical location).
This is the detail that I missed in REV-00. I just mapped everything at $0000 assuming the software knew that $0100 was the CMOS location. The problem with this implementation is that writes to $1100 will overwrite the CMOS at $0100 as they aren't directed to different physical locations. This is why System 7 will never work on the REV-00 board and requires a revision.
</tl;dr>
As mentioned above I do not plan to spend too much time on this as I still have outstanding big boards to build. I just need to take a small break from that to recharge. If you're still waiting for a board I will resume building within a few days.