Quoted from oyvindmo:
Btw, do anyone know for sure where the 60/50Hz protection is implemented? If it's on the CPU sub-board, which seems likely, we should be able to swap that module between the MPU boards and get up and running. [quoted image]
I asked a friend at work (who designs hardware for a living) about how he would go about designing a 50/60Hz + region lock. The answer was this:
1) "Incorporate a tiny step down transformer that is sampled by the microcontroller ADC. This will provide line frequency information."
There is a signal name called ADC_INT (ADC interrupt ?) this is connected to GPIO3_27 according to information in the schematics near the bottom of the EDM-1 page (rev E). (GPIO3_IO27 in NXP the data sheet)
2) "Use one of the GPIO pins (via a pull-up or pull-down resistor) to configure the board as a european or US board"
The data sheet for the onboard NXP application processor (MCIMX6U5DVM10AC) specifies that it has boot mode configuration fuses (and also pins that can override these fuses). Again - if we look at EDM-1 (rev E), we see that one of these boot fuses is referenced (but without specified usage in the schematic). This is BOOT_CFG2 (EIM_DA8)
Looking at the CPU schematic, EIM_DA8 is connected as an input port named EIM_DA8/7.7E, so it is reasonable to assume that there is a signal to this pin that is routed somewhere on the PCB. This pin is internally connected to a 100k pull-up, so I guess that a natural way of achieving hardware region coding during manufacture is by adding a zero ohm resistor between EIM_DA8/7.7E and GND somewhere_ on the board.
However, in addition to the boot option fuses, the NXP also has a BT_FUSE_SEL fuse that determines if the GPIO pins can override the boot option fuses. Even if the assumptions in this post are correct, everything depends on the state of the BT_FUSE_SEL fuse.
Just my two cents